TU Wien:High-Level Synthesis VU (Müller-Gritschneder)

Daten

Zuordnungen

Masterstudium Technische Informatik

Modul Advanced Design and Synthesis of Digital Systems

Inhalt

• High Level Synthesis (HLS)
  • compiler frontend (how to get from C code to an intermediate representation)
  • compiler optimizations
  • HLS algorithms to automatically...
    • go from intermediate representation to RTL
    • derive resource allocation and timing from the intermediate representation
    • derive control logic
    • generate results to meet timing or resource constraints
• Computer Architecture (RISC-V)
  • Dynamic Branch Prediction
  • Out-of-Order execution
  • Super-scalar/-pipelining Processor
  • Heterogeneous SoCs
    • Vector Processors, SIMD
    • GPUs/TPUs/NPUs

Ablauf

Weekly lectures with example exercises the first part is about HLS algorithms, followed by an overview of advanced computer architecture topics. There is a homework assignment for each part.

In parallel to the first part there is an HLS Lab to get to try a HLS tool in practice (Vivado HLS).

Benötigte/Empfehlenswerte Vorkenntnisse

noch offen

Vortrag

noch offen

Übungen

noch offen

Prüfung, Benotung

noch offen

Dauer der Zeugnisausstellung

noch offen

Zeitaufwand

noch offen

Unterlagen

noch offen

Tipps

noch offen

Highlights / Lob

noch offen

Verbesserungsvorschläge / Kritik

noch offen

Materialien

Diese Seite hat noch keine Anhänge, du kannst aber neue hinzufügen.