TU Wien:Advanced Digital Design LU (Steininger)

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Lecturers Florian Ferdinand HuemerJürgen MaierAndreas Steininger
ECTS 1,5
Alias Advanced Digital Design (en)
When winter semester
Last iteration 2021WS
Language English
Mattermost advanced-digital-designRegisterMattermost-Infos
Links tiss:182754, Homepage
Master Technische Informatik Wahlmodul Digital Circuits and Systems


Inhalte aus der VU tatsächlich auf einem FPGA beobachten/implementieren.

metastability, clock domain crossing, asynchronous design


There are 2 assignments which include implementing easy designs on a FPGA and measurements with the logic analyzer and oscilloscope. The results are presented by each group (3 students) to all the other groups in a 10-15 min presentation + discussion per assignment.

Benötigte/Empfehlenswerte Vorkenntnisse[edit]

Basic VHDL skills

TU Wien:Digital Design VO (Steininger)

in parallel: TU Wien:Advanced Digital Design VU (Steininger)


  1. Assignment
    1. Metastability measurements of a D-Flip-Flop
    2. Clock domain crossing: what problems can you encounter and how to prevent them
  2. Assignment
    1. Introduction to Workcraft
    2. Build an controller for speed independent codes (represented by LEDs)
    3. Implement a delay insensitive communication link (-> data is sent via UART to the FPGA transmitted asynchronously on the chip and via IO pins to allow LA measurements and then sent back via UART)

Prüfung, Benotung[edit]

The quality of the solution and especially the presentations are used for the final score.

Dauer der Zeugnisausstellung[edit]

noch offen




noch offen


Start early, then you have enough time for other procrastinated stuff in January

If you have any problems, ask the LVA-team they can always help

Verbesserungsvorschläge / Kritik[edit]

noch offen


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