TU Wien:Advanced Digital Design LU (Steininger)

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Daten[Bearbeiten | Quelltext bearbeiten]

Vortragende Florian Ferdinand HuemerAndreas Steininger
ECTS 1,5
Letzte Abhaltung 2023W
Sprache English
Mattermost advanced-digital-designRegisterMattermost-Infos
Links tiss:182754
Masterstudium Technische Informatik Modul Digital Circuits and Systems (Gebundenes Wahlfach)

Inhalt[Bearbeiten | Quelltext bearbeiten]

Inhalte aus der VU tatsächlich auf einem FPGA beobachten/implementieren.

metastability, clock domain crossing, asynchronous design, STGs

Ablauf[Bearbeiten | Quelltext bearbeiten]

There are 2 assignments which include implementing easy designs on a FPGA and measurements with the logic analyzer and oscilloscope. The results are presented by each group (3 students) to all the other groups in a 10-15 min presentation + discussion per assignment.

WS22: There were 3 assignments, where the first was measurment with the logic analyzer and oscilloscope. The second only needed the FPGA dev board and the last one needed the oscilloscope. The assignment were not easy but also not very hard. At the end of the semester each group presented their results which also led to small discussions between all groups and the professor.

Benötigte/Empfehlenswerte Vorkenntnisse[Bearbeiten | Quelltext bearbeiten]

Basic VHDL skills

TU Wien:Digital Design VO (Steininger)

in parallel: TU Wien:Advanced Digital Design VU (Steininger)

Übungen[Bearbeiten | Quelltext bearbeiten]

  1. Assignment
    1. Metastability measurements of a D-Flip-Flop
    2. Clock domain crossing: what problems can you encounter and how to prevent them
  2. Assignment
    1. Introduction to Workcraft
    2. Build an controller for speed independent codes (represented by LEDs)
    3. Implement a delay insensitive communication link (-> data is sent via UART to the FPGA transmitted asynchronously on the chip and via IO pins to allow LA measurements and then sent back via UART)


  1. Assignment: Metastability measurement of a D-Flip-Flop, Clock domain crossing of a data stream
  2. Assignment: LED pattern generator with STGs
  3. Assignment: QDI adder pipeline

Prüfung, Benotung[Bearbeiten | Quelltext bearbeiten]

The quality of the solution and especially the presentations are used for the final score.

Dauer der Zeugnisausstellung[Bearbeiten | Quelltext bearbeiten]

WS22: 12 days

Zeitaufwand[Bearbeiten | Quelltext bearbeiten]


Unterlagen[Bearbeiten | Quelltext bearbeiten]

noch offen

Tipps[Bearbeiten | Quelltext bearbeiten]

Start early, then you have enough time for other procrastinated stuff in January. Also start early because there is only one FPGA dev board with oscilloscope and logic analyzer which otherwise you have to share with the other groups.

If you have any problems, ask the LVA-team they can always help

Highlights / Lob[Bearbeiten | Quelltext bearbeiten]

noch offen

Verbesserungsvorschläge / Kritik[Bearbeiten | Quelltext bearbeiten]

noch offen


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